ginngi engineering

In this project a FPGA based H.264 decoder was implemented. In surveillance systems there is a need to view the video of numerous cameras on a single screen. H.264 video compression has become the de-facto standard in such systems, replacing older, less efficient MPEG4 standards. The decoding and rendering of H.264 streams is very time-intensive requiring enormous computing power. Typical PC platforms are limited in their ability to meet these requirements, especially in light of the newer High-Definition standard, which requires eight times more computing power than Standard Definition.

A multi-channel H.264 network decoder was implemented using an architecture consisting of a Davinci DSP/ARM and a Xilinx Virtex-5 FPGA. A RTSP/RTCP/RTP client was implemented under Linux, which provided raw H.264 streams to the FPGA. The FPGA decoded the H.264 streams into respective YUV streams and passed it back to the Davinci DSP, which performed rendering and interfacing to a HDMI controller, which drove a LCD screen.

The FPGA was coded in VHDL and simulated under Modelsim.