ginngi engineering

In digital surveillance video cameras the latency incurred to filter and compress video must not be noticeable to an end user who is used to using analog systems that incur no delays. Today's cameras typically use H.264 video compression, which can consume enormous computing time and contribute to significant latencies. To reduce latencies a custom FPGA was implemented that performs noise filtering, deinterlacing and H.264 compression interfacing to a Davinci DSP.

A custom FPGA (Virtex-5) was implemented to perform noise filtering, deinterlacing, H.264 video compression and a streaming interface to a Davinci DSP. The noise filter was designed using Impulse C technology, which was both modeled and coded in C. The deinterlacer model was written in C and implemented and simulated in VHDL. The deinterlacer uses a dynamic spatial-temporal motion detection algorithm to determine the value of pixels on odd lines of the frame resulting in either a Bob, Weave or combination of the two all on a pixel by pixel basis. The H.264 compressor is an off-the-shelf core, which implements the H.264 Baseline encoding standard.

The project followed the classical design model consisting of Architectural Analysis, Design, C-bit Accurate Modelling, RTL Coding, Module Simulation, and chip Verification, written in VHDL and using Modelsim simulation tools.