ginngi engineering

An FPGA core was implemented to perform deinterlacing of standard definition video prior to its being compressed and streamed onto a network. Existing algorithms using simple Bob/Weave approaches were rejected because of their poor performance during scenes that have movement. The resulting design uses a sophisticated algorithm that performs pixel computation based on a spatial-temporal model and motion detection, all on a pixel-by-pixel basis. The design was successfully implemented on a Virtex-5 FPGA.

Virtually all Standard Definition cameras provide video in an interlaced format consisting of two fields separated in time by half a frame time (20 msec). In high-movement scenes this causes distortion and loss of visual quality, which was deemed unacceptable for our customer's video network encoder. An algorithm was developed which computes each pixel for the odd field of the frame using a complex function consisting of a two dimensional spatial filter and a temporal filter. The final pixel value is therefore a dynamic function of the state of the pixels surrounding the current pixel both is space and time, which results in a superior deinterlaced image.

In addition to the algorithm itself an infrastructure was developed that allowed for the flow of pixels in real time. This included designing an efficient DDR controller to save intermediate data, a scheduler for smartly managing the saving and retrieving of data in real-time, various FIFOs to relieve timing bottlenecks and the use of DSP blocks for the algorithm intensive operations.

The algorithm was modeled in C, implemented in VHDL and simulated under ModelSim.